Capacitors and inductors represent two types of on-chip passive devices commonly employed in many types of monolithic integrated circuits designed to operate at high frequencies, such as those found in wireless communication devices. In particular, on-chip passive devices are found in radiofrequency integrated circuits (RFICs), which have applications such as Phase-Locked Loop (PLL) transmitters, voltage controlled oscillators (VCOs), impedance matching networks, filters, etc. The integration of on-chip capacitors and inductors is accomplished by introducing these passive devices into one or more of the metallization levels of the back-end-of-line (BEOL) wiring structure, which are used to electrically connect the active devices fabricated using the semiconductor substrate during front-end-of-line (FEOL) processing. A popular method of forming a BEOL wiring structure is a dual damascene process in which vias and trenches in various dielectric layers are filled with metal in the same process step to create multi-level, high density metal interconnections.
Relevant parameters characterizing on-chip inductors include inductance and the quality factor Q. The quality factor Q, which is a commonly accepted indicator of inductor performance in an RFIC, represents a measure of the relationship between energy loss and energy storage. Parasitic capacitance and parasitic resistance from eddy current losses are generated between the conductors forming the on-chip inductor and the semiconductor substrate. A high value for the quality factor, Q, reflects low energy losses to the substrate. To that end, conventional BEOL wiring structures may rely on a Faraday shield at the first metal (M1) level to optimize substrate isolation of on-chip inductors.
Despite their usefulness, on-chip passive devices tend to make rather inefficient use of the surface area in the BEOL wiring structure. In particular, completely separate areas are used for each on-chip inductor and each on-chip capacitor. As a result, the area available in the BEOL wiring structure for the conductive paths actually used to connect the active devices is reduced.
Improved fabrication techniques are needed for forming compact BEOL wiring structures that overcome problems associated with the conventional inefficiencies in the use of chip area and other deficiencies of conventional techniques for fabricating conventional BEOL wiring structures that include an on-chip capacitor and an on-chip inductor.